A memory module generally comprises a plurality of integrated memory chips soldered on a memory module circuit board. Moreover, further integrated chips, containing for example registers, buffers and a phase locked loop (PLL), may be arranged on the circuit board of the memory module. In order to be able to connect the memory module to a computing unit, the memory module circuit board has connections along one of its longitudinal sides. These connections can then be used to plug the memory module as main memory, for example, into a PC receptacle provided therefor. The various embodiments of the memory modules are standardized in module families and available with different storage capacities.
Single inline memory modules (SIMMs), for example, form one of the standardized embodiments. They have 72 connections and are available either with a data width of 32 bits for applications without a parity bit or with a data width of 36 bits for applications with a parity bit. So-called dual inline memory modules (DIMMs) represent a further standard in the module families of the memory modules and are a further development of the SIMM family. By comparison with the SIMM modules, in which the integrated memory chips are arranged only on one side of the circuit board, the integrated memory chips can be arranged on the front and rear sides of the circuit board in the case of the DIMM modules. DIMM modules have, for example, 168 connections or even more connections, half of them being arranged on the front side and the other half thereof being arranged on the rear side of the circuit board. The DIMM modules have the advantage of double the data width, inter alia, by comparison with SIMM modules.
Buffered DIMM modules and also non-buffered DIMM modules are known. The buffered DIMM modules are equipped with a buffer which, by means of an integrated buffer chip, amplifies the address, command and clock signals which are used to drive the individual integrated memory chips on the DIMM module. As a result, it is possible to reduce unavoidable input capacitances. This is important primarily when the intention is to realize systems having many receptacles for DIMM modules, as is the case with servers, for example. So-called registered DIMM modules represent a further development of buffered DIMM modules. In the case of registered DIMM modules, the address and command signals are amplified by integrated register chips, while the clock signals are amplified by an integrated clock supply chip containing a phase locked loop. The clock supply chip with the phase locked loop also simultaneously serves for driving the registers in order that the address and command signals to be accepted are stored in the registers in a correctly timed manner.
Dynamic memories, also referred to as dynamic random access memory (DRAM), are generally used as integrated memory chips.
Since the phase locked loop in the integrated chip operates only within a specific frequency range, for example around +/−30% above or below the typical operating frequency of the PLL, the registered DIMM module cannot be operated or tested at a frequency which lies below the lower limiting frequency of the phase locked loop.
A typical productive test program also encompasses, inter alia, the retention time, that is to say the time duration during which data are maintained in a dynamic memory chip (DRAM) without renewed refreshing. The detection of the retention time requires long test times, which are independent of the operating frequency of the integrated memory chip. In principle, during tests it is desirable to test the memory chips on cost-effective test systems, but the latter can only provide low test frequencies. The consequence of this, however, is that the phase locked loop no longer operates properly. Therefore, the tests must necessarily be carried out with the aid of expensive test systems, which can provide the clock frequency required for operation of the PLL. The productive test is regularly effected during or at the end of the production of the DIMM modules in order to ascertain the functionality thereof and to determine their specification.
In the event of analyzing registered DIMM modules for defects, for example in order to determine the cause of a failure of the module or its components in the event of a return from the customer, the defect analysis is carried out by means of a more cost-effective test system, which can therefore only provide low clock frequencies. In this case, for the defect analysis, the relevant integrated memory chips have to be unordered from the registered DIMM module and be individually tested. On the one hand, the desoldering operation is associated with a considerable expenditure of time. On the other hand, parameters within the memory chip may be attenuated again or even eliminated, inter alia, as a result of annealing, which makes the analysis more difficult or impossible.